Job Details

Are you a Lead Layout Design Engineer who is seeking am amazing opportunity delivering disruptive High Speed Interconnect Technology powering next generation AI? We are looking for a Lead Layout Design Engineer – someone who is excited to join a fast growing Start-Up Company growing a group of diverse individuals responsible for handling high-speed mixed-signal circuit designs!

Preferred Location - On-Site at our Irvine, Ca HQ

What You Will Do:

• The role entails working collaboratively and multi-functionally with a multi-disciplinary team of Exceptional Analog Mixed Signal Design Engineers, DSP, Electronics, and Systems engineers
• Conduct chip layout circuit design, circuit checking, and device evaluation and characterization.
• Responsible for chip floorplan, routing, chip assembly, and back-end verification across multiple projects. Perform physical layout for mixed-signal functions like PLL's, high speed ADC, DAC circuits, ESD structures designs in state-of-the-art sub-micron < 5nm CMOS technologies using Cadence tools
• You'll work with talented DSP and mixed-signal engineers to customize designs for integration in high speed SERDES products
• Job duties will include floor planning, custom layout and verifying against design rules and schematics. Fill, post-processing, DRC mitigation, and foundry interactions
• Experience in <5nm Process Technologies is strongly preferred.

What You Will Bring:

• Minimum of Technical Training or BSEE preferred w/ 10+ years of Analog Layout Design experience, 4+ years leading Junior Layout Engineer.

• Understanding of the Semiconductor Fabrication process and device/layout cross-sections.

• Experience with FinFET processes (3nm, 5nm, 7nm, etc.).

• Several tape-outs with FinFETs owning major layout macros (ADC / DAC / PLLs) or the chip.

• Experience with block/macro floor-planning, block integration, routing, clock distribution, and power grid implementation.

• Understanding of ESDs and clamps, and their layout considerations.

• Understanding of layout effects such as LOD/OSE/PSE/WPE/MBE/LDE.

• Expert-level knowledge of layout considerations for device matching, symmetry, parasitic reduction, and noise isolation.

• Expert-level knowledge of running and debugging LVS/ERC/DRC/Density/DFM/Antenna verifications.

• Expert-level knowledge of Cadence Virtuoso and Calibre (or Synopsys design and verification tools).

• Experience working with revision-controlled design libraries.

• Experience with supervising/mentoring junior Layout Designers.

• Experience working with remote International teams in different time zones.

• Excellent communication skills.

• Knowledge of SKILL, TCL, and Python scripting is a plus.